MTD 132; A new sub-nanosecond multi-hit CMOS time-to-digital converter
This paper describes a new 8 channel, 16 hit, sub-nanosecond resolution, 16 bit dynamic range time-to- digital VLSI CMOS circuit. It can operate in either common start or common stop mode and records either leading, trailing, or both input edges. Double pulse resolution is 15 ns. Readout is sparsifi...
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Veröffentlicht in: | IEEE transactions on nuclear science 1991-04, Vol.38:2 |
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Hauptverfasser: | , , , , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This paper describes a new 8 channel, 16 hit, sub-nanosecond resolution, 16 bit dynamic range time-to- digital VLSI CMOS circuit. It can operate in either common start or common stop mode and records either leading, trailing, or both input edges. Double pulse resolution is 15 ns. Readout is sparsified, and input signal levels are ECL while control and output levels are CMOS. Measured performance of prototype devices is presented. A CAMAC and a FASTBUS TDC board using this chip are under development. |
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ISSN: | 0018-9499 1558-1578 |
DOI: | 10.1109/23.289279 |