Comparison of Four Cell Topologies for 1.2-kV Accumulation- and Inversion-Channel 4H-SiC MOSFETs: Analysis and Experimental Results

The electrical characteristics of 1.2-kV-rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs with linear, square, hexagonal, and octagonal cell topologies fabricated using the same design rules and process flow in a 6-in foundry are compared for the first time. TCAD numerical simulat...

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Veröffentlicht in:IEEE transactions on electron devices 2019-05, Vol.66 (5), p.2321-2326
Hauptverfasser: Han, Kijeong, Baliga, B. J.
Format: Artikel
Sprache:eng
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Zusammenfassung:The electrical characteristics of 1.2-kV-rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs with linear, square, hexagonal, and octagonal cell topologies fabricated using the same design rules and process flow in a 6-in foundry are compared for the first time. TCAD numerical simulations have been conducted to analyze the structures. For all the cell topologies, it was found that the Acc MOSFETs have lower specific ON-resistance ( {R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}} ) than the Inv counterparts due to higher channel mobility resulting in 1.3- 2.0\times smaller high-frequency figure-of-merit (HF-FOM[ {R} _{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}} ]), where {Q} _{\textsf {gd}} is the gate-to-drain charge. It is observed that the square and hexagonal cell topologies with the same structural dimensions show similar electrical performance. When compared with the standard linear cell topology: 1) the hexagonal cell topology has 1.15\times better specific ON-resistance and 1.12\times worse HF-FOM[ \text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}} ] and 2) the octagonal cell topology has 1.5\times worse specific ON-resistance and 1.4\times better HF-FOM[ \text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}} ]. In addition, the octagonal cell topology has a much superior figure-of-merit (FOM[ {C} _{\textsf {iss}}/{C} _{\textsf {rss}} ]), where {C} _{\textsf {iss}} is the input capacitance and {C} _{\textsf {gd}} is the reverse transfer capacitance.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2019.2905736