A Reference Clock Doubler with Fully Digital Duty-cycle Error Correction Controller

In this paper, a clock frequency doubler capable of handling large variation in input duty cycle and PVT (Process, Voltage and Temperature) is presented. Clock doubler with XOR gate cannot be used if the duty of the input clock is not 50 %. A circuit that calibrates the duty to 50 % is added in front of the clock doubler, the clock doubler has a low jitter and doubles the frequency even if the duty of the input clock is not 50 %. The fully digital method proposed in this paper overcomes the disadvantages of the existing analog methods, such as standby current and large area due to the use of capacitors and amplifiers, to enable low-current, low-area implementation. The reference clock doubler is implemented using 55-nm CMOS process and the die area is 80 mu m x 80 mu m. The power consumption is 30 mu W under the supply voltage of 1 V. Measured maximum duty cycle error correction range and average frequency error are +/- 30 % and less than 0.5 %, respectively.