Impact of Strategic Approaches for Improving the Device Performance of Mesa-shaped Nanoscale Vertical-Channel Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Zn–O Channel Layers

The effect of two strategic approaches, such as modification of active layer geometry and control of active channel composition, were investigated to improve the on/off ratio (I ON /I OFF ) and field-effect mobility (µ FE ) of mesa-shaped nanoscale vertical-channel thin-film-transistor (VTFT). The SiO 2 spacer was deposited by using plasma-enhanced chemical vapor deposition and patterned via plasma etching process with Ar/CF 4 gas mixtures to form a vertical sidewall, corresponding to a channel length of 170 nm. The gate-stack structures including an In–Ga–Zn–O (IGZO) active layer were deposited by atomic layer deposition with a complete conformality along the spacer sidewall. The I ON /I OFF of the IGZO VTFT was significantly enhanced from 6.7 × 10 3 to 2.1 × 10 9 by lowering the off-state current when the layout geometry of active layer was properly designed to eliminate the uncontrolled current path between the vertically separated source and drain (S/D) electrodes. Furthermore, the µ FE was improved from 0.3 to 2.2 cm 2 /Vs by enhancing the I ON when the In/Ga ratio increased to 1.4 by controlling the In contents within the IGZO active channel. The device also showed robust stabilities under positive/negative gate-bias stresses at 2 MV/cm for 10 4 s. However, still low a µ FE was suggested to originate from two detrimental issues of back-channel effects on spacer sidewall and contact resistance between the channel and S/D electrodes. Alternatively, it was confirmed that the increase in indium contents within the IGZO channel could be a useful way to reduce the contact resistance between the channel and S/D electrodes. Graphical Abstract