Implementation of In–Ga–Zn–O Thin-Film Transistors with Vertical Channel Structures Designed with Atomic-Layer Deposition and Silicon Spacer Steps

Vertical channel thin film transistors (VTFTs) using silicon (Si) spacer steps and In–Ga–Zn–O (IGZO) active channels were demonstrated. The Si spacer step was strategically introduced from the viewpoint of a new structural design to secure the surface quality of the back-channel region of the nanoscale IGZO VTFTs. The vertical sidewalls of the Si spacer were patterned via plasma etching technique using CF 4 /O 2 gas mixtures with controlled process conditions. The atomic layer deposition (ALD) was found to be one of the most important process parameters to obtain promising device operations of the fabricated IGZO VTFTs. The device parameters of drain current on/off ratio, carrier mobility at linear region, and subthresholde swing for the IGZO VTFT with a channel length of 250 nm were obtained to be 6.9 × 10 7 , 3.21 cm 2 /Vs, and 460 mV/dec, respectively. The fabricated VTFT also showed negligible variations in threshold voltage against the gate bias stresses of ± 1 MV/cm for 10 4 s. The introduction of Si spacer steps and the IGZO channels prepared by conformal ALD could be presented as effective methodologies for implementing highly-functional nanoscale IGZO VTFTs. Graphic Abstract