Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction
Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock schedul...
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Veröffentlicht in: | Journal of semiconductor technology and science 2009, 8(1), , pp.29-36 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Power supply noise is fundamentally caused
by large current peaks. Since large current peaks are
induced by simultaneous switching of many circuit
elements, power supply noise can be minimized by
deliberate clock scheduling which utilizes nonzero clock
skew. In this paper, nonzero skew clock scheduling is
used to avoid the large peak current and consequently
reduce power supply noise. While previous approaches
require extra characterization efforts to acquire current
waveform of a circuit, we approximate it only with
existing cell library information to be easily adapted
to conventional design flow. A simulated annealing based
algorithm is performed, and the peak current values
are estimated for feasible clock schedules found by the
algorithm. The clock schedule with the minimum peak
current is selected for a solution. Experimental results
on ISCAS89 benchmark circuits show that the proposed
method can effectively reduce the peak current. KCI Citation Count: 1 |
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ISSN: | 1598-1657 2233-4866 |
DOI: | 10.5573/JSTS.2009.9.1.029 |