A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference

This work describes a 13b 100 MS/s 0.13um CMOS four-stage pipeline ADC for 3Gcommunication systems. The proposed SHA-freeADC employs a range-scaling technique based onswitched-capacitor circuits to properly handle a wideinput range of 2VP-P using a single on-chip referenceof 1VP-P. The proposed range scaling makes thereference buffers keep a sufficient voltage headroomand doubles the offset tolerance of a latchedcomparator in the flash ADC1 with a doubled inputrange. A two-step reference selection technique in theback-end 5b flash ADC reduces both powerdissipation and chip area by 50%. The prototypeADC in a 0.13 um CMOS demonstrates the measureddifferential and integral nonlinearities within 0.57LSB and 0.99 LSB, respectively. The ADC shows amaximum signal-to-noise-and-distortion ratio of64.6 dB and a maximum spurious-free dynamic rangeof 74.0 dB at 100 MS/s, respectively. The ADC with anactive die area of 1.2 mm2 consumes 145.6 mWincluding high-speed reference buffers and 91 mWexcluding buffers at 100 MS/s and a 1.3 V supplyvoltage. KCI Citation Count: 4