Efficient Multi-site Testing Using ATE Channel Sharing

Multi-site testing is considered as a solutionto reduce test costs. This paper presents a newchannel sharing architecture that enables I/O pins toshare automatic test equipment (ATE) channels usingsimple circuitry such as tri-state buffers, AND gates,and multiple-input signature registers (MISR). Themain advantage of the proposed architecture is that itis implemented on probe cards and does not requireany additional circuitry on a target device under test(DUT). In addition, the proposed architecture canperform DC parametric testing of the DUT such asleakage testing, even if the different DUTs share thesame ATE channels. The simulation results show thatthe proposed architecture is very efficient and isapplicable to both wafer testing and package testing. KCI Citation Count: 2