A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

In this paper, a clock and data recovery(CDR) circuit that supports triple data rates of 1.62,2.7, and 5.4 Gbps for DisplayPort 1.2 standard isdescribed. The proposed CDR circuit covers threedifferent operating frequencies with a single VCOswitching the operating frequency by the 3-bit digitalcode. The prototype chip has been designed andverified using a 65 nm CMOS technology. Therecovered-clock jitter with the data rates of1.62/2.7/5.4 Gbps at 231-1 PRBS is measured to7/5.6/4.7 psrms, respectively, while consuming 11 mWfrom a 1.2 V supply. KCI Citation Count: 1