Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dBΩ and 12 GHz, respectively. 20-Gb/s 231−1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10−12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage. KCI Citation Count: 1