Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDS and Low VGS/High VDS in Amorphous InGaZnO Thin-Film Transistors

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high VGS/low VDS and low VGS/high VDS stress conditions through incorporating a forward/reverse VGS sweep and a low/high VDS readout conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high VGS/low VDS stress is applied. On the other hand, when low VGS/high VDS stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high VGS/low VDS stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low VGS/high VDS stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a- IGZO bottom-gate TFT becomes complicatedly modulated during the positive VGS/VDS stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane. KCI Citation Count: 1