Area-efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors

We present a transposable crossbar synapse memory using 6T SRAM bit cell to speed up online learning of neuromorphic processors at minimal area cost. Based on the proposed integrated transposable row addressing scheme using a row-transition multiplexer, fast write and read operations are made possible for both row-wise and column-wise accesses in an integrated 6T SRAM bit cell array at much smaller area cost compared to the previous works. A 256×256 4-bit transposable synapse memory was implemented in a 28 nm CMOS technology, which had 26% area overhead against the non-transposable 6T synapse memory. The estimated performance gains for unsupervised learning algorithms of spiking neural network and restricted Boltzmann machine using the MNIST data set were 6.3× and 19.3× respectively compared to the non-transposable synapse memory. KCI Citation Count: 2