High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel

This paper proposes a high-performance, low-complexity, soft-decision Bose–Chaudhuri–Hocquenghem (SD-BCH) decoder architecture and its efficient design techniques. The proposed SD-BCH decoder not only uses the test syndrome computation, but also non-iteration processes. The proposed (1020, 990) SD-BCH decoder achieves a 0.75 dB higher coding gain compared to the (1020, 990) hard-decision BCH (HD-BCH) decoder. The proposed SD-BCH decoder was designed and implemented using the 65-nm CMOS technology. The synthesis results show that the proposed SD-BCH decoder architecture with serial structure (P = 1) has 24.7K gate count, which leads to a 69% reduction in hardware complexity compared to the previous SD-BCH decoder architecture. KCI Citation Count: 0