CMOS true‐time delay IC for wideband phased‐array antenna

This paper presents a true‐time delay (TTD) using a commercial 0.13‐μm CMOS process for wideband phased‐array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7‐bit TTD circuit, and a 6‐bit digital step attenuator (DSA) circuit. The T‐type attenuator with a low‐pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time‐delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz–18 GHz. The maximum time delay of 198 ps with a 1.56‐ps step and the maximum attenuation of 31.5 dB with a 0.5‐dB step are achieved at 2 GHz–18 GHz. The RMS time‐delay and amplitude errors are