High-performance Parallel Concatenated Polar-CRC Decoder Architecture

In this paper, a novel parallel encoding and decoding method is proposed, which uses concatenated polar-cyclic redundancy check (polar-CRC) codes for high throughput polar decoder implementation. When compared to previous works, the proposed method considerably reduces latency and improves throughput. A parallel concatenated polar-CRC decoder architecture based on the proposed method is presented and synthesized using 65-nm CMOS process technology. Synthesis results show that the proposed architecture has 4.9 times the data throughput and 4.5 times the hardware efficiency of conventional SC polar decoder architecture. KCI Citation Count: 0