Functional-power-aware Partial Gating Method for Low Power Scan-shift

This paper presents a new scheme to minimize scan-shift power for test reliability with minimized functional power overhead, which is achieved by selective insertion of signal gating-logic considering the loading condition and switching activity of scan shift signals. The proposed methodology also considers practical design issues such as logic-timing overhead and cell-congestion impact associated with scan-shift power reduction. In experimental results with industrial system-on-chip (SoC) designs, the proposed power-aware gating-logic-insertion methodology not only achieved reduction of scan-shift power but also improved functional power up to 10% compared with the conventional full-scan gating scheme. KCI Citation Count: 0