Dual-port SDRAM Architecture for Low-power Communication of Internet-of-things Devices

In this paper, we propose a dual-port SDRAM architecture as an energy-efficient inter-processor communication solution tailored to Internet-of-Things (IoTs) devices. Since a single memory chip plays the role of the local memories and the shared memory for both processors, it gives a simpler solution than a typical architecture that uses an additional dual-port SRAM as shared memory. To minimize the non-negligible synchronization overhead, we also propose two optimization techniques by exploiting the communication patterns of a target application: lock-priority and static-copy. Experiments on a virtual prototyping system show promising results, in which we achieved about 25-50% performance gain as well as about 40% power saving from the proposed optimization techniques compared with the existing architecture. KCI Citation Count: 1