Charging Effect of a Nano-Floating Gate Capacitor with Double-Layered Au Nano-Particles
A nano-floating gate capacitor with double-layered Au nano-particles embedded in a SiO1:3N layer was fabricated and characterized. The Au nano-particles were formed from Au thin film with a nominal thickness of 1 nm and their average size and density were about 4 nm and 2 × 1012 cm-2, respectively....
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Veröffentlicht in: | Journal of the Korean Physical Society 2008, 53(3), , pp.1484-1487 |
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Hauptverfasser: | , , , , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | A nano-floating gate capacitor with double-layered Au nano-particles embedded in a SiO1:3N layer was fabricated and characterized. The Au nano-particles were formed from Au thin film with a nominal thickness of 1 nm and their average size and density were about 4 nm and 2 × 1012 cm-2, respectively. After the post-annealing process at 800 ℃ for 10 s, the
flat-band voltage shift of the nano-floating gate capacitor with double-layered Au nano-particles was about 9 V when the applied gate voltage was swept from -10 V to +10 V. Signicantly, the flat-band voltage shifts were improved after the post-annealing process. The double-layered Au nano-particles embedded in a SiO1:3N dielectric showed feasibility as nano-floating gate capacitors for nonvolatile memories. KCI Citation Count: 2 |
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ISSN: | 0374-4884 1976-8524 |
DOI: | 10.3938/jkps.53.1484 |