The Bias Stress Effect on Poly-Silicon TFTs
We investigated the gate-bias stress effect on N-channel and P-channel poly-silicon thin-film transistors (p-Si TFT). We measured the changes in the transfer characteristics with gate-bias stress and investigated effect of the temperature on recovery. After observing a positive gate-bias stress with...
Gespeichert in:
Veröffentlicht in: | Journal of the Korean Physical Society 2009, 54(1), , pp.484-488 |
---|---|
Hauptverfasser: | , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | We investigated the gate-bias stress effect on N-channel and P-channel poly-silicon thin-film transistors (p-Si TFT). We measured the changes in the transfer characteristics with gate-bias stress and investigated effect of the temperature on recovery. After observing a positive gate-bias stress with zero-drain voltage, we observed a negative threshold voltage shift and measured its recovery characteristics for annealing temperatures up to 320 ℃. A negative shift of the transfer curve was observed during positive gate-bias stress with a zero drain-voltage. The negative shift is attributed to a positive charge near the interface of the poly-silicon and the silicon dioxide; this result differs from the results of a hot-electron bias-stress experiment. A decrease in the mobility was also observed during the gate-bias stress with zero drain-voltage. From the recovery annealing experiment, we concluded that the defects associated with the positive charge were created during positive charge generation. The recovery annealing temperature was as high as around 200 ℃ due to defects associated with the positive charge. We investigated the gate-bias stress effect on N-channel and P-channel poly-silicon thin-film transistors (p-Si TFT). We measured the changes in the transfer characteristics with gate-bias stress and investigated effect of the temperature on recovery. After observing a positive gate-bias stress with zero-drain voltage, we observed a negative threshold voltage shift and measured its recovery characteristics for annealing temperatures up to 320 ℃. A negative shift of the transfer curve was observed during positive gate-bias stress with a zero drain-voltage. The negative shift is attributed to a positive charge near the interface of the poly-silicon and the silicon dioxide; this result differs from the results of a hot-electron bias-stress experiment. A decrease in the mobility was also observed during the gate-bias stress with zero drain-voltage. From the recovery annealing experiment, we concluded that the defects associated with the positive charge were created during positive charge generation. The recovery annealing temperature was as high as around 200 ℃ due to defects associated with the positive charge. KCI Citation Count: 3 |
---|---|
ISSN: | 0374-4884 1976-8524 |
DOI: | 10.3938/jkps.54.484 |