Design optimization of vertical double-gate tunneling field-effect transistors

In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High- k materials such as Si 3 N 4 , HfO 2 , and ZrO 2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high- k material (L high- k ) and the thickness of silicon channel (t Si ). For HfO 2 , the subthreshold swing ( SS ) and on-current were optimized at a L high -k of 11 nm and a t Si of 5 nm. The optimized device had an on-current ( I on ) of 151 µA/µm and a SS of 46.6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.