A single-phase, nine-level switched-capacitor-based inverter

The conventional topological approach to eliminate the multiple-input DC voltage requirement in multilevel inverter configurations for synthesizing high-output voltage levels is to deploy split capacitor banks at the input terminal. This method stipulates a less expensive, light weight, and reduced size inverter system. However, the excessive demand for several capacitor banks and the complex voltage balancing strategy associated with this conceptual approach poses numerous limitations in their deployment. In view of these drawbacks, this study proposes a self-balanced, single-phase, nine-level switched-capacitor-based inverter topology consisting of a single-input DC voltage, an auxiliary circuit, and an H-bridge circuit unit. A commensurate single carrier-based sinusoidal pulse-width modulation scheme is developed for the proposed power circuit control, enabling the synthesis of a nine-level output voltage waveform whose amplitude is four times the input voltage value. Detailed power circuit operations and switching functions are adequately provided in the proposed topology. A comparison between the proposed inverter and its recent counterparts in terms of component count, cost involvement, and output voltage-boosting ability is duly carried out using Python data visualization. Results reveal that the proposed inverter competes well in these three criteria. For varying R–L load values, the inverter has the capability of high active and reactive power delivery. Its dynamic response for step changes in the modulation index under these power-mode operations is presented in this paper. For high active power-mode operation, efficiencies of 98.27% and 98.92% under light- and heavy-load conditions, respectively, are obtained on a 3-kW-rated inverter prototype.