Charge-trap memory effect in spray deposited ZnO-based electrolyte-gated transistors operating at low voltage

Charge-trap memory phenomena were demonstrated in an electrolyte-gated transistor (EGT) using a spray-coated zinc oxide (ZnO) active layer and a cellulose-based electrolyte. The EGT exhibited efficient programming and erasing characteristics at low voltages, shifting the threshold voltage and the magnitude of the on-current. This behavior is discussed in terms of the influence of charged trapping states at the ZnO/electrolyte interface and within the ZnO bulk. The presence of these traps leads to a shift in the mobility from 0.57 ± 0.16 cm2 V−1 s−1 in the initial state to 0.02 ± 0.01 cm2 V−1 s−1 when programmed. Retention experiments revealed improved stability of the memory state when a low positive voltage is applied to the gate, indicating that the device's characteristics are extremely sensitive to the trapping/detrapping of charges at the semiconductor/electrolyte interface. Capacitance spectroscopy measurements using planar and metal-insulator-semiconductor configurations within the same device were used to analyze the charging dynamics of the trap states at different programming states. [Display omitted] •A solution-based route was successfully used for fabricating the memory transistor suitable for printed electronics.•The memory transistor presented an effective low-voltage programming and erasing feature that shifts the device parameters.•Trapping/detrapping of charges at the ZnO/electrolyte interface and within the ZnO bulk influenced the device behavior.•Capacitance spectroscopy measurements provided insights into the charging dynamics of trap states at the different stages.