Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction
In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be...
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| Veröffentlicht in: | Journal of semiconductor technology and science 2023, 23(4), 112, pp.207-214 |
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| Hauptverfasser: | , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. KCI Citation Count: 0 |
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| ISSN: | 1598-1657 2233-4866 2233-4866 1598-1657 |
| DOI: | 10.5573/JSTS.2023.23.4.207 |