Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Ieee Transactions On Electron Devices 2022-04, Vol.69 (6), p.3113-3117
Hauptverfasser: Liu, Hsiao-Hsuan, Salahuddin, Shairfe M, Abdi, Dawit, Chen, Rongmei, Weckx, Pieter, Matagne, Philippe, Catthoor, Francky
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique.
ISSN:0018-9383