Selective Metal Deposition for Advanced Metallization Schemes

Starting from critical dimensions below 10 nm, the continuation of CMOS scaling requires the Cu replacement as an IC interconnect material by a barrierless metal with lower resistivity and better electromigration performance than Cu. Co and Ru are currently considered to be the most attractive candidates for the Cu replacement as they offer a tradeoff between material properties, cost, precursor and manufacturing processes availability. In addition, narrow dimensions of interconnect features require implementation of bottom-up metal fill schemes to mitigate defects in metal structures such as voids and seams. At the same time, significant technological improvements are required to mitigate the pattern overlays and litho-based edge placement errors when forming multilevel structures with a half-pitch at or below 10 nm. The transition from standard multiple litho-etch deposition schemes to bottom-up area-selective deposition (ASD) is a very promising way to enable self-alignment of multilevel structures. Integrating bottom-up area-selective building-blocks in a microelectronic processing flow has a disruptive potential because of the unique capability of engineering new structures and architectures, through selective growth in one area over other areas. The approaches to achieve selectivity of the (metal) deposition can be classified in three categories: i) intrinsic selectivity, ii) selectivity enabled by passivation of the "non-growth area" and iii) selectivity enabled by activation of the "growth area". Among deposition processes, electroless deposition (ELD) and atomic layer deposition (ALD) can be effectively used in selective deposition schemes due to their chemical nature and surface sensitivity. This work explores all three categories of ASD approaches for BEOL technology application, utilizing the above listed deposition techniques and metals, considered as promising candidates for Cu replacement. Intrinsically selective metal deposition can be realized for very limited number of material combinations used in IC manufacturing process flow. The surface functionality of a "growth area" must be favorable for metal ALD, while the surface termination of "non-growth area" of the substrate must simultaneously inhibit ALD nucleation. This work focuses on various H-based plasma treatments, which allow forming appropriate surface functionalities enabling selective ALD nucleation and growth in one area of the substrate, while ALD is blocked in the other part o