Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40nm CMOS

This work presents a near-threshold operating voltage timing error detecting 32-bit microcontroller system. The lightweight in situ EDAC technique uses a soft-edge flip-flop combined with in-latch transition detection and a set-dominant error latch to detect datapath transitions after the clock edge. Inherent error correction is achieved through time borrowing in soft-edge flip-flops. The technique is implemented in an ARM Cortex M0 microcontroller system in 40nm CMOS, rendering the microcontroller 'timing error aware'. Automatic critical path analysis results in an optimized timing error detection window and sparse flip-flop replacement. An autonomous DVS loop facilitates automatic operation at the point-of-first-failure. The M0 system operates down to 290mV and achieves 11-18pJ/cycle core energy consumption in a 5-30MHz frequency range. The architecture profits optimally from ULV operation at frequencies