A 16.07pJ/cycle 31MHz Fully Differential Transmission Gate Logic ARM Cortex M0 core in 40nm CMOS

This paper presents a 16.07pJ/cycle 31MHz ARM Cortex M0 core in 40nm CMOS. The system was designed using differential transmission gates in an extended standard cell flow, taking into account variability, speed, energy and scalability. Extensive measurements over a range of 25 dies show it achieves sub-20pJ/cycle operation in a 330-500mV 10-48MHz range and is fully functional down to 190mV. Compared to state-of-the-art, a 40x speed and 4.8x EDP improvement is reported at the MEP. With low variation (σ/μ) on the clock frequency (3.5% at the MEP) and energy consumption (18.2% at the MEP), it combines the low variability, high speed and low energy of full custom work with the ease and design time of standard cell design.