Saturation Photo-Voltage Methodology for Semiconductor/Insulator Interface Trap Spectroscopy

The presence of large densities of electrically active defects is still an unsolved issue for future high-mobility/high-k CMOS device technologies. This relates to degraded device performance and reliability.Regrettably, conventional admittance-based characterization techniques often fail when applied to non-Si based devices. Among others, enhanced generation of minority carriers and much longer defect time constants make their results inaccurate. Rather than of seeking to adapt commonly-used techniques, we instead aim at direct measuring the semiconductor surface potential by means of the Saturation surface PhotoVoltage (SPV) technique. This approach allows for a DIT estimation which is not limited by the trap response time or hindered by minority carrier generation. Moreover, the DIT can be estimated over the whole bandgap regardless of sample doping type.We here report several case studies in support of the proposed approach. We will also show that SPV can be applied for the characterization of multi-layered Ge and III-V devices incorporating high-k insulators.