Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-κ Spacer Technology

We propose a novel optimized design strategy by considering the correlated effects of $high-{\kappa}$ gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	Journal of semiconductor technology and science 2018, Vol.18 (3), p.295-300
Hauptverfasser:	Jang, Esan, Shin, Sunhae, Jeong, Jae Won, Kim, Kyung Rok
Format:	Artikel
Sprache:	kor
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!