Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-κ Spacer Technology

We propose a novel optimized design strategy by considering the correlated effects of $high-{\kappa}$ gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical to lateral direction in 14-nm InAs n-FinFET and Ge p-FinFET with abrupt and high drain doping, the lateral GIDL is suppressed as 1/100 by $high-{\kappa}$ spacer with high drive current of 1 mA/um and lower leakage current than 100 nA/um which works on lower operation voltage ($V_{DD}=0.63V$). in addition, DIBL is also suppressed below 100 mV/V by taking relatively $lower-{\kappa}$ gate oxide than the $high-{\kappa}$ spacer.