Nano and microfilled conducting adhesives for zaxis interconnections new direction for highspeed, highdensity, organic microelectronics packaging

Purpose The purpose of this paper is to discuss the use of epoxybased conducting adhesives in zaxis interconnections. Designmethodologyapproach A variety of conductive adhesives with particle sizes ranging from 80nm to 15m were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the microstructures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90 peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IRreflow, thermal cycling, pressure cooker test PCT, and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling DTC between 55 and 125C. Findings The volume resistivity of copper, silver and lowmelting point LMP alloy based paste were 5104, 5105 and 2105cm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTCtreated Cu as high as 2.75lbsin. for silver, and as low as 1.00lbin. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IRreflow, PCT, and solder shock. Among all, silverbased adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silverfilled paste decreased due to sintering of metal particles. Research limitationsapplications As a case study, an example of silverfilled conductive adhesives as a zaxis interconnect construction for a flipchip plastic ball grid array package with a 150m die pad pitch is given. Originalityvalue A highperformance Zinterconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multichip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.