Saturation of threshold-voltage shift during positive bias temperature instability in HfSiON/SiO2 n-channel MOSFET and its effect on device lifetime evaluation

This paper investigates the saturation of threshold-voltage shift ΔVth of HfSiON/SiO2 n-channel MOSFETs (nMOFSETs) under positive bias temperature instability (PBTI) and proposes an empirical PBTI degradation model that can predict operational lifetime tL accurately. Experimental results indicate that secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law ΔVth ∝ tn as the gate stress voltage Vg,str increases. This dependency of n on Vg,str results in overestimation of tL when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of Vg,str on n is proposed; this model predicted operational tL = 2.6 × 105 s, which agreed well with experimentally-measured tL = 3.9 × 105 s.