Impact of additional Pt and NiSi crystal orientation on channel stress induced by Ni silicide film in metal-oxide-semiconductor field-effect transistors

The impact of additional Pt and Ni monosilicide (NiSi) crystal orientation on channel stress from Ni silicide in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been demonstrated. The channel stress generation mechanism can be explained by the NiSi crystal orientation. In pure Ni silicide films, the channel stress in the p-type substrate is much larger than that in the n-type one, since the NiSi a-axis parallel to the channel direction is strongly aligned on the p-type substrate compared with on the n-type one. On the other hand, in NiPt silicide films, the difference in the channel stress between the p- and n-type substrates is small, because the NiSi crystal orientation on the p-type substrate is similar to that on the n-type one. These results can be explained by the Pt segregation at the interface between the NiSi film and the Si surface. Segregated Pt atoms cause the NiSi b-axis to align normal to the Si(001) surface in the nucleation step owing to the expansion of the NiSi lattice spacing at the NiSi/Si interface. Furthermore, the Pt segregation mechanism is considered to be caused by the grain boundary diffusion in the Ni2Si film during NiSi formation. We confirmed that the grains of Ni2Si on the p-type substrate are smaller than those on the n-type one. The Ni2Si film on the p-type substrate has more grain boundary diffusion paths than that on the n-type one. Therefore, the amount of Pt segregation at the NiSi/Si interface on the p-type substrate is larger than that on the n-type one. Consequently, the number of NiSi grains with the b-axis aligned normal to the Si(001) in the p-type substrate is larger than that in the n-type one. As a result, the channel stress induced by NiPt silicide in PMOS is larger than that in NMOS. According to this mechanism, controlling the Pt concentration at the NiSi/Si interface is one of the key factors for channel stress engineering.