Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration
We demonstrate chip-level integrated n-type metal-insulator-semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the...
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| Veröffentlicht in: | Japanese Journal of Applied Physics 2020-08, Vol.59 (8), p.1 |
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| container_title | Japanese Journal of Applied Physics |
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| creator | Matsuura, Kentaro Hamada, Masaya Hamada, Takuya Tanigawa, Haruki Sakamoto, Takuro Hori, Atsushi Muneta, Iriya Kawanago, Takamasa Kakushima, Kuniyuki Tsutsui, Kazuo Ogura, Atsushi Wakabayashi, Hitoshi |
| description | We demonstrate chip-level integrated n-type metal-insulator-semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future. |
| doi_str_mv | 10.35848/1347-4065/aba9a3 |
| format | Article |
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The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.</description><identifier>ISSN: 0021-4922</identifier><identifier>EISSN: 1347-4065</identifier><identifier>DOI: 10.35848/1347-4065/aba9a3</identifier><identifier>CODEN: JJAPB6</identifier><language>eng</language><publisher>Tokyo: IOP Publishing</publisher><subject>2D-FETs ; Aluminum oxide ; Electrodes ; Energy consumption ; Field effect transistors ; Forming gas annealing ; Lithography ; MIS (semiconductors) ; Molybdenum disulfide ; N-type semiconductors ; Normally-off ; Semiconductor devices ; Semiconductors ; Sputtering ; Sulfur powder annealing ; Titanium nitride ; Transition metal di-chalcogenide ; Two dimensional materials</subject><ispartof>Japanese Journal of Applied Physics, 2020-08, Vol.59 (8), p.1</ispartof><rights>2020 The Japan Society of Applied Physics</rights><rights>Copyright Japanese Journal of Applied Physics Aug 1, 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0003-2008-7695 ; 0000-0002-5830-5283</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.35848/1347-4065/aba9a3/pdf$$EPDF$$P50$$Giop$$Hfree_for_read</linktopdf><link.rule.ids>314,776,780,27901,27902,53821,53868</link.rule.ids></links><search><creatorcontrib>Matsuura, Kentaro</creatorcontrib><creatorcontrib>Hamada, Masaya</creatorcontrib><creatorcontrib>Hamada, Takuya</creatorcontrib><creatorcontrib>Tanigawa, Haruki</creatorcontrib><creatorcontrib>Sakamoto, Takuro</creatorcontrib><creatorcontrib>Hori, Atsushi</creatorcontrib><creatorcontrib>Muneta, Iriya</creatorcontrib><creatorcontrib>Kawanago, Takamasa</creatorcontrib><creatorcontrib>Kakushima, Kuniyuki</creatorcontrib><creatorcontrib>Tsutsui, Kazuo</creatorcontrib><creatorcontrib>Ogura, Atsushi</creatorcontrib><creatorcontrib>Wakabayashi, Hitoshi</creatorcontrib><title>Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration</title><title>Japanese Journal of Applied Physics</title><addtitle>Jpn. J. Appl. Phys</addtitle><description>We demonstrate chip-level integrated n-type metal-insulator-semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.</description><subject>2D-FETs</subject><subject>Aluminum oxide</subject><subject>Electrodes</subject><subject>Energy consumption</subject><subject>Field effect transistors</subject><subject>Forming gas annealing</subject><subject>Lithography</subject><subject>MIS (semiconductors)</subject><subject>Molybdenum disulfide</subject><subject>N-type semiconductors</subject><subject>Normally-off</subject><subject>Semiconductor devices</subject><subject>Semiconductors</subject><subject>Sputtering</subject><subject>Sulfur powder annealing</subject><subject>Titanium nitride</subject><subject>Transition metal di-chalcogenide</subject><subject>Two dimensional materials</subject><issn>0021-4922</issn><issn>1347-4065</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>O3W</sourceid><recordid>eNptkDtPwzAQgC0EEqXwA9gssbCY-pXEGVHFo1ILQ8tsOYndOjKxSVxQF347LkWwIJ3u5PN3PvkD4JLgG5YJLiaE8QJxnGcTValSsSMw-m0dgxHGlCBeUnoKzoahTcc842QEPp98_6qc2yFvDBzCNkbd6wYt_JLCbjFb3t-tBvhh4wau7BOMPqC1ihpqp-vY-0bDNAwbbWynG1jtoA_R1spBl0b8uldhs4PG97De2ICcftcO2i7qdBOt787BiVFu0Bc_dQxe0sLpI5o_P8ymt3NkicgZqrlKUVJSsJw3FefCiILWFcdM8ILXSpFMGaN0ZmrOSNnkmpqqNDr9WpA8Y2NwdXg39P5tq4coW7_tu7RSUr4XmDJOFDpQ1oc_gGD5rVjufcq9T3lQnPjrf_i2VUFmpRQSC1ziXIbGsC9pIn39</recordid><startdate>20200801</startdate><enddate>20200801</enddate><creator>Matsuura, Kentaro</creator><creator>Hamada, Masaya</creator><creator>Hamada, Takuya</creator><creator>Tanigawa, Haruki</creator><creator>Sakamoto, Takuro</creator><creator>Hori, Atsushi</creator><creator>Muneta, Iriya</creator><creator>Kawanago, Takamasa</creator><creator>Kakushima, Kuniyuki</creator><creator>Tsutsui, Kazuo</creator><creator>Ogura, Atsushi</creator><creator>Wakabayashi, Hitoshi</creator><general>IOP Publishing</general><general>Japanese Journal of Applied Physics</general><scope>O3W</scope><scope>TSCCA</scope><scope>7U5</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2008-7695</orcidid><orcidid>https://orcid.org/0000-0002-5830-5283</orcidid></search><sort><creationdate>20200801</creationdate><title>Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration</title><author>Matsuura, Kentaro ; Hamada, Masaya ; Hamada, Takuya ; Tanigawa, Haruki ; Sakamoto, Takuro ; Hori, Atsushi ; Muneta, Iriya ; Kawanago, Takamasa ; Kakushima, Kuniyuki ; Tsutsui, Kazuo ; Ogura, Atsushi ; Wakabayashi, Hitoshi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1863-c4ac4a9217364db448f872cb4038474caa15affae5fc4319d6e2fb9fe02181653</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>2D-FETs</topic><topic>Aluminum oxide</topic><topic>Electrodes</topic><topic>Energy consumption</topic><topic>Field effect transistors</topic><topic>Forming gas annealing</topic><topic>Lithography</topic><topic>MIS (semiconductors)</topic><topic>Molybdenum disulfide</topic><topic>N-type semiconductors</topic><topic>Normally-off</topic><topic>Semiconductor devices</topic><topic>Semiconductors</topic><topic>Sputtering</topic><topic>Sulfur powder annealing</topic><topic>Titanium nitride</topic><topic>Transition metal di-chalcogenide</topic><topic>Two dimensional materials</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Matsuura, Kentaro</creatorcontrib><creatorcontrib>Hamada, Masaya</creatorcontrib><creatorcontrib>Hamada, Takuya</creatorcontrib><creatorcontrib>Tanigawa, Haruki</creatorcontrib><creatorcontrib>Sakamoto, Takuro</creatorcontrib><creatorcontrib>Hori, Atsushi</creatorcontrib><creatorcontrib>Muneta, Iriya</creatorcontrib><creatorcontrib>Kawanago, Takamasa</creatorcontrib><creatorcontrib>Kakushima, Kuniyuki</creatorcontrib><creatorcontrib>Tsutsui, Kazuo</creatorcontrib><creatorcontrib>Ogura, Atsushi</creatorcontrib><creatorcontrib>Wakabayashi, Hitoshi</creatorcontrib><collection>IOP Publishing Free Content</collection><collection>IOPscience (Open Access)</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Japanese Journal of Applied Physics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Matsuura, Kentaro</au><au>Hamada, Masaya</au><au>Hamada, Takuya</au><au>Tanigawa, Haruki</au><au>Sakamoto, Takuro</au><au>Hori, Atsushi</au><au>Muneta, Iriya</au><au>Kawanago, Takamasa</au><au>Kakushima, Kuniyuki</au><au>Tsutsui, Kazuo</au><au>Ogura, Atsushi</au><au>Wakabayashi, Hitoshi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration</atitle><jtitle>Japanese Journal of Applied Physics</jtitle><addtitle>Jpn. J. Appl. Phys</addtitle><date>2020-08-01</date><risdate>2020</risdate><volume>59</volume><issue>8</issue><spage>1</spage><pages>1-</pages><issn>0021-4922</issn><eissn>1347-4065</eissn><coden>JJAPB6</coden><abstract>We demonstrate chip-level integrated n-type metal-insulator-semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. 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| subjects | 2D-FETs Aluminum oxide Electrodes Energy consumption Field effect transistors Forming gas annealing Lithography MIS (semiconductors) Molybdenum disulfide N-type semiconductors Normally-off Semiconductor devices Semiconductors Sputtering Sulfur powder annealing Titanium nitride Transition metal di-chalcogenide Two dimensional materials |
| title | Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration |
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