(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NF MIN ) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS will play a significant role in the 6G infrastructure, in particular for communications in the D-band spectrum (110-170 GHz), for which the challenge at HBT level is to demonstrate maximum oscillation frequency f MAX > 500 GHz. Benefitting from mature CMOS technologies, the smallest CMOS node used in BiCMOS chips is the 45 nm partially depleted silicon on insulator [1]. STMicroelectronics has been using the 55 nm node since 2014 [2]. These nodes are today sufficient to address the digital content of the targeted circuits, while offering the right performance/cost trade-off. Although the HBT performance depends on lateral scaling too, it is mainly driven by the 1D dopant profile. Multiple Si and SiGe layers are grown by Reduced Pressure-Chemical Vapor Deposition (RP-CVD) epitaxy, defining the core of the device. For a self-aligned architecture such as STMicroelectronics’ EXBIC architecture, four epitaxy steps with different doping levels are required (Fig. 1) [3]. Improvement of key electrical parameters such as NF MIN and f MAX depends on the optimization of these epitaxies. Specifically, the collector epitaxy can be performed by non-selective or selective epitaxy, each with its advantages and drawbacks. Non-selective epitaxy is performed early in the BiCMOS process flow, with no thermal budget impact on the CMOS process. This kind of epitaxy is also cheaper but can cause auto-doping at the epitaxial interface [4] and put constraints on the collector integration, that are solved by the selective epitaxy of the collector. This scheme is used in the latest devices from both STMicroelectronics [3] and GlobalFoundries [5]. The transit time of electrons through the base is determined by its thickness and its composition. Significant performance gains have been achieved by switching from pure Si to a graded SiGe base architecture. The bandgap variation due to the graded SiGe