(Invited) Engineering Semiconducting and Dielectric Materials and Processes Using Integrative Methods

Plasma-based unit processes are at the core of process technology, enabling future nanosheet and nanowire-based logic. Patterning must deliver pristine surfaces at an atomic scale over films with strict geometric, interfacial, and material property (RI, density, WER, leakage) requirements. Still a silicon world, it is giving way to new materials including 2D structures and dielectrics. Patterning is no longer planar; it is now 3D with plasma process having to grapple with hidden geometries rather than simply lines, spaces, and holes. There is no shortage of challenges to the realization of new device technology. Process hardware options come with increased degrees of freedom. At the same time, however, new options introduce mechanistic complexity that burdens engineering development. Empirical methods alone cannot be used to grapple with current challenges. Integrative methods extend the old concept of concurrent engineering. In this approach, a combination of first principles simulation and experiments targets important unknowns of process and hardware development rather than seek a system level (“simulation-of-everything”) description. First principles simulations include so-called quantum chemistry methods, while first principles experiments include diagnostics that relate species flux directly with surface reactions (for removal or addition) and materials properties. Clarity to the least understood aspects of critical processes is the desired outcome. This leads to a vehicle for understanding what species flux-surface reactions are needed to achieve structures, and films and then ultimately what processes are needed to achieve them. How dielectric films meet many requirements at the same time given process trade-offs is an example of where clarity is needed. From a singular process, geometric requirements, etch resistance, and mechanical and electrical properties must be met and have long lasting integrity. Three component and non-silicon dielectrics, less understood due to their newness in mainstream device manufacturing, are also of current interest. The imperative for a quantitative understanding of process trade-offs for etch is present across all etch technologies. Our integrative approach is described in this presentation. Beyond a discussion of methodology, the presentation will highlight several examples. One related to silicon carbon nitride (SiCN) dielectric film deposition illustrates the trade-offs among leakage current, refractive index, a