(Invited) Hybrid Bonding for 3D Applications: Improvements and Limitations

Wafer direct bonding has attracted considerable concerns since it takes advantage of the ability to achieve strong adherence between flat, clean, and smooth surface without the use of intermediate materials. This technology experienced a consequent rise with the More than Moore's law. With this...

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Veröffentlicht in:Meeting abstracts (Electrochemical Society) 2023-12, Vol.MA2023-02 (33), p.1592-1592
Hauptverfasser: Deloffre, Emilie, Ayoub, Bassel, Lhostis, Sandrine, Dettoni, Florent, Fournel, Frank, Montméat, Pierre, Mermoz, Sebastien
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Sprache:eng
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Zusammenfassung:Wafer direct bonding has attracted considerable concerns since it takes advantage of the ability to achieve strong adherence between flat, clean, and smooth surface without the use of intermediate materials. This technology experienced a consequent rise with the More than Moore's law. With this trend, added value to devices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Law”. Indeed, this aims to realize three-dimensional (3D) integration systems by stacking devices and interconnecting them using Through-Silicon-Via (TSV) or Cu-Cu interconnections. Hybrid bonding is preferred to other chip stacking technologies because Cu-Cu hybrid bonding is easily capable of scaling down and present excellent reliability results. Hybrid bonding is key technology to address several applications especially images sensor. Even more specialized applications or better performances could be obtained through hybrid bonding pitch reduction [1]. High quality bonding for 3D technology has been demonstrated using an accurate wafer bonding tool with optimized metrology [2]. The total overlay values reached is below 110 nm with residuals values below 80 nm and scaling inferior to 0.5 ppm for interconnect pitches from 6.9 µm down to 0.6 µm. The electrical properties have been checked and confirmed the robustness of the fine pitch hybrid bonding module and the stability of the bonding interface [3]. The latest process and hardware developments have made it possible to greatly reduce scaling. However, distortion remains the most complicated parameter to optimize. It is strongly linked to the design of the chip (number of metal levels, stress...). Today, a minimum critical dimension design rule should be respected to avoid short between front side and backside layers and this is preventing pixel shrink. To reduce pixel size, distortion value needs to be decreased. For that purpose, in situ monitoring of the bonding wave is necessary as well as bonding chucks multiple vacuum zones in order to achieve homogenous bonding wave propagation. Even if hybrid bonding integration and performance have been considerably improved, we can notice that thermal budget is a main limitation for this technology. Indeed, to reach strong bonding energy which is mandatory for subsequent mechanical manufacturing; a bonding anneal of 800°C is required. By using plasma treatment prior bonding, anneal temperature can be decreased to 400°C. However, some devices can
ISSN:2151-2043
2151-2035
DOI:10.1149/MA2023-02331592mtgabs