On the Characteristics of Traps and Charges in the Si/SiO2/HfO2/TaN High-k Gate Stacks

High-k gate stacks were fabricated with the p-Si/graded-SiO2/HfO2/TaN configuration; control samples were fabricated with the p-Si/graded-SiO2/TaN configuration. A host of device parameters were extracted from the measured admittance data, including the gate stack capacitance density, the surface potential in the accumulation regime, the standard deviation of the surface potential, the interface trap density, trap energy, and trap capture cross-section, the flatband charge density in the SiO2 intermediate layer, the flatband charge density in the HfO2 high-k layer, and the accumulation surface potential coefficient, many of which were extracted for the first time for the high-k gate stacks. The experimental results provided new information on the nature of defects (interface traps and bulk charges) in the SiO2 intermediate layer and in the HfO2 high-k layer.