SRAF Optimization for sub-40nm Technology Node Contact Patterning

As 193nm immersion lithography is extended to sub-40nm technology node, how to define a single-pass contact hole patterning process with enough common lithography process window is a very challenging task. Sub-resolution assist features (SRAF) optimization is one crucial step besides illumination optimization and mask bias optimization. This paper presents a comprehensive SRAF optimization flow that achieves a set of SRAF solutions that balances SRAF benefits and mask manufacturing feasibility. As the criterion of patterning performance, the through pitch process window is investigated for different SRAF placement options based on simulated PV-band of a given process variation (focus & dose). Full chip optimization with representative layouts is also studied. Silicon level performance verification is done with final SRAF solution for through pitch pattern and typical layouts. Finally, we conclude the paper by demonstrating the overall benefit of SRAF on CD uniformity, from process capability as well as mask complexity perspectives.