Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates

We present for the first time the successful fabrication of Ω-gate P-type FETs with epitaxial compressively-strained SiGe (Ge=30%) on tensily-strained SOI substrates. The recess down to the strained-Si etch-stop layer in the source/drain (S/D) areas (after spacer etching) followed by a selective epitaxy of in-situ boron-doped Si0.7Ge0.3 raised S/Ds allowed us to offset the performance loss due to tensile strain in short gate length Si0.7Ge0.3/sSi NW devices. The hole mobility improvement resulting from the compressive strain and VTH shift between Si0.7Ge0.3/sSi and Si channel transistors led to an ION current improvement of +100% at LG=15nm compared to SOI, providing a promising path for performant CMOS integration.