Method for disclosing invisible physical properties in metal−ferroelectric−insulator−semiconductor gate stacks

In metal-ferroelectric-insulator-semiconductor gate stacks of ferroelectric-gate field effect transistors (FeFETs), it is impossible to directly obtain curves of polarization versus electric field (Pf−Ef) in the ferroelectric layer. The Pf−Ef behavior is not simple, i.e. the Pf−Ef curves are hysteretic and nonlinear, and the hysteresis curve width depends on the electric field scan amplitude. Unless the Pf−Ef relation is known, the field Ef strength cannot be solved when the voltage is applied between the gate meal and the semiconductor substrate, and thus Pf−Ef cannot be obtained after all. In this paper, the method for disclosing the relationships among the polarization peak-to-peak amplitude (2Pmm_av), the electric field peak-to-peak amplitude (2Emm_av), and the memory window (Ew) in units of the electric field is presented. To get Pmm_av versus Emm_av, FeFETs with different ferroelectric-layer thicknesses should be prepared. Knowing such essential physical parameters is helpful and in many cases enough to quantitatively understand the behavior of FeFETs. The method is applied to three groups. The first one consists of SrBi2Ta2O9-based FeFETs. The second and third ones consist of CaxSr1−xBi2Ta2O9-based FeFETs made by two kinds of annealing. The method can clearly differentiate the characters of the three groups. By applying the method, ferroelectric relationships among Pmm_av, Emm_av, and Ew are well classified in the three groups according to the difference of the material kinds and the annealing conditions. The method also evaluates equivalent oxide thickness (EOT) of a dual layer of a deposited high-k insulator and a thermally-grown SiO2-like interfacial layer (IL). The IL thickness calculated by the method is consistent with cross-sectional image of the FeFETs observed by a transmission electron microscope. The method successfully discloses individual characteristics of the ferroelectric and the insulator layers hidden in the gate stack of a FeFET.