Implementation of efficient strategies for cell generation in VLSI design

The problem of automatic layout synthesis is addressed. Given a description of the cell circuit to be synthesized and a set of constraints the layout must satisfy, the problem is to generate automatically the corresponding layout through the placement and interconnections of all the circuit elements. The resulting layout is a symbolic one, in the sense that only the relative positions of objects are defined to make the layout independent of design rules. This layout synthesis problem can be efficiently solved by implementing a set of suitable heuristic strategies, and the user can influence the functioning of the cell generator by defining some layout compilation options. The solutions obtained represent good trade-offs between area minimization and circuit performance optimization.