Microprocessor based simulation and digital logic model of gate turn-off thyristor

A digital logic model of a gate turn-off thyristor is developed considering the turn-on and turn-off mechanisms of the device. A commonly used R-C-D snubber circuit is also included in the proposed model. Relations between different delay times, e.g. storage time, Tall time, turn-off time and tail time, become apparent from the model. The model is simulated with the help of a microprocessor to establish the validity of the proposal.