Effect of ITCs on gate stacked JL-TFET based on work-function engineering

A stacked double gate junctionless tunnel field-effect transistor (JL-TFET) has been proposed and examined the effects of interface trap charges (ITCs) by introducing both acceptor and donor charges at the semiconductor/insulator interface. The structure uses two isolated gates (polarity gate and control gate) over an n-type-doped silicon substrate to function as a TFET. The effect of ITCs has been analysed in terms of DC and analogue/radio-frequency performance using parameters such as transfer characteristics, electric field, electric potential, transconductance (gm) for both conventional and gate stacked JL-TFET. Additionally, they have also analysed metrics used to measure the device linearity performance and intermodulation distortion such as higher-order transconductance coefficients (gm2, gm3) and figure of merit. All the simulations have been performed with the help of an Atlas device simulator.