Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.