Fine-grained hardware switching scheme for power reduction in multiplication

Fine-grained hardware switching scheme for power reduction in multiplication

This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduct...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Electronics letters 2016-08, Vol.52 (16), p.1374-1375
Hauptverfasser: Huang, Y, Li, C, Li, M, Van der Perre, L, Dehaene, W
Format: Artikel
Sprache:eng
Schlagworte:
Circuits and systems
Computation
Computer simulation
Electronics
execution unit
fine‐grained hardware switching scheme
gate‐level simulation
Hardware
low power computing
low‐power electronics
Multiplication
multiplication unit
OpenRISC
Optimization
power reduction
reduced instruction set computing
Reduction
Switching
word‐length optimisation opportunities
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduction for the multiplication unit, which accounts for 9.5% power reduction for its execution unit.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2015.3828