Substrate parasitic extraction for RF integrated circuits
Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | 1107 |
| container_title | |
| container_volume | |
| creator | Cathelin, A. Leclercq, Y. Saias, D. Belot, D. Clement, F.R.J. |
| description | Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor. |
| doi_str_mv | 10.1109/DATE.2002.998463 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_998463</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>998463</ieee_id><sourcerecordid>31538279</sourcerecordid><originalsourceid>FETCH-LOGICAL-i205t-530bdd48d2a824aaa1a946efbe8bcc29a323b447bc53bae8a02fc1b9d68f058f3</originalsourceid><addsrcrecordid>eNotkE1Lw0AQhhc_wLZ6F085eUvcz2T3WGqrQkHQeg6zm4mspE3c3YD-e1PqaWCeh3eYl5BbRgvGqHl4XO7WBaeUF8ZoWYozMmNK6XyC7JzMaVUaxWTF1MURCJozZdgVmcf4RSlVgpsZMe-jjSlAwmyAANEn7zL8mTYu-f6QtX3I3jaZPyT8PFpN5nxwo0_xmly20EW8-Z8L8rFZ71bP-fb16WW13OaeU5Xy6a5tGqkbDppLAGBgZImtRW2d4wYEF1bKyjolLKAGylvHrGlK3VKlW7Eg96fcIfTfI8ZU73102HVwwH6MtZhe07wyk3h3Ej0i1kPwewi_9aka8QfGnFZ3</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>31538279</pqid></control><display><type>conference_proceeding</type><title>Substrate parasitic extraction for RF integrated circuits</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Cathelin, A. ; Leclercq, Y. ; Saias, D. ; Belot, D. ; Clement, F.R.J.</creator><creatorcontrib>Cathelin, A. ; Leclercq, Y. ; Saias, D. ; Belot, D. ; Clement, F.R.J.</creatorcontrib><description>Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.</description><identifier>ISSN: 1530-1591</identifier><identifier>ISBN: 0769514715</identifier><identifier>ISBN: 9780769514710</identifier><identifier>EISSN: 1558-1101</identifier><identifier>DOI: 10.1109/DATE.2002.998463</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic testing ; Circuit simulation ; Design automation ; Europe ; Frequency measurement ; Radio frequency ; Radiofrequency integrated circuits ; RF signals ; Signal design</subject><ispartof>Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, 2002, p.1107</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/998463$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,25140,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/998463$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Cathelin, A.</creatorcontrib><creatorcontrib>Leclercq, Y.</creatorcontrib><creatorcontrib>Saias, D.</creatorcontrib><creatorcontrib>Belot, D.</creatorcontrib><creatorcontrib>Clement, F.R.J.</creatorcontrib><title>Substrate parasitic extraction for RF integrated circuits</title><title>Proceedings - Design, Automation, and Test in Europe Conference and Exhibition</title><addtitle>DATE</addtitle><description>Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.</description><subject>Automatic testing</subject><subject>Circuit simulation</subject><subject>Design automation</subject><subject>Europe</subject><subject>Frequency measurement</subject><subject>Radio frequency</subject><subject>Radiofrequency integrated circuits</subject><subject>RF signals</subject><subject>Signal design</subject><issn>1530-1591</issn><issn>1558-1101</issn><isbn>0769514715</isbn><isbn>9780769514710</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkE1Lw0AQhhc_wLZ6F085eUvcz2T3WGqrQkHQeg6zm4mspE3c3YD-e1PqaWCeh3eYl5BbRgvGqHl4XO7WBaeUF8ZoWYozMmNK6XyC7JzMaVUaxWTF1MURCJozZdgVmcf4RSlVgpsZMe-jjSlAwmyAANEn7zL8mTYu-f6QtX3I3jaZPyT8PFpN5nxwo0_xmly20EW8-Z8L8rFZ71bP-fb16WW13OaeU5Xy6a5tGqkbDppLAGBgZImtRW2d4wYEF1bKyjolLKAGylvHrGlK3VKlW7Eg96fcIfTfI8ZU73102HVwwH6MtZhe07wyk3h3Ej0i1kPwewi_9aka8QfGnFZ3</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Cathelin, A.</creator><creator>Leclercq, Y.</creator><creator>Saias, D.</creator><creator>Belot, D.</creator><creator>Clement, F.R.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>2002</creationdate><title>Substrate parasitic extraction for RF integrated circuits</title><author>Cathelin, A. ; Leclercq, Y. ; Saias, D. ; Belot, D. ; Clement, F.R.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i205t-530bdd48d2a824aaa1a946efbe8bcc29a323b447bc53bae8a02fc1b9d68f058f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Automatic testing</topic><topic>Circuit simulation</topic><topic>Design automation</topic><topic>Europe</topic><topic>Frequency measurement</topic><topic>Radio frequency</topic><topic>Radiofrequency integrated circuits</topic><topic>RF signals</topic><topic>Signal design</topic><toplevel>online_resources</toplevel><creatorcontrib>Cathelin, A.</creatorcontrib><creatorcontrib>Leclercq, Y.</creatorcontrib><creatorcontrib>Saias, D.</creatorcontrib><creatorcontrib>Belot, D.</creatorcontrib><creatorcontrib>Clement, F.R.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cathelin, A.</au><au>Leclercq, Y.</au><au>Saias, D.</au><au>Belot, D.</au><au>Clement, F.R.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Substrate parasitic extraction for RF integrated circuits</atitle><btitle>Proceedings - Design, Automation, and Test in Europe Conference and Exhibition</btitle><stitle>DATE</stitle><date>2002</date><risdate>2002</risdate><spage>1107</spage><pages>1107-</pages><issn>1530-1591</issn><eissn>1558-1101</eissn><isbn>0769514715</isbn><isbn>9780769514710</isbn><abstract>Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.</abstract><pub>IEEE</pub><doi>10.1109/DATE.2002.998463</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1530-1591 |
| ispartof | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, 2002, p.1107 |
| issn | 1530-1591 1558-1101 |
| language | eng |
| recordid | cdi_ieee_primary_998463 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic testing Circuit simulation Design automation Europe Frequency measurement Radio frequency Radiofrequency integrated circuits RF signals Signal design |
| title | Substrate parasitic extraction for RF integrated circuits |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T22%3A45%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Substrate%20parasitic%20extraction%20for%20RF%20integrated%20circuits&rft.btitle=Proceedings%20-%20Design,%20Automation,%20and%20Test%20in%20Europe%20Conference%20and%20Exhibition&rft.au=Cathelin,%20A.&rft.date=2002&rft.spage=1107&rft.pages=1107-&rft.issn=1530-1591&rft.eissn=1558-1101&rft.isbn=0769514715&rft.isbn_list=9780769514710&rft_id=info:doi/10.1109/DATE.2002.998463&rft_dat=%3Cproquest_6IE%3E31538279%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=31538279&rft_id=info:pmid/&rft_ieee_id=998463&rfr_iscdi=true |