Substrate parasitic extraction for RF integrated circuits

Substrate parasitic extraction for RF integrated circuits

Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed...

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Bibliographische Detailangaben
Hauptverfasser: Cathelin, A., Leclercq, Y., Saias, D., Belot, D., Clement, F.R.J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Automatic testing
Circuit simulation
Design automation
Europe
Frequency measurement
Radio frequency
Radiofrequency integrated circuits
RF signals
Signal design
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Beschreibung
Zusammenfassung:Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2002.998463