A Fractional- N Synthesizer Based on Programmable Frequency Multiplier for 5G ^ Communication System

This article presents a new fractional- N frequency synthesizer for 5G ^{+} communication systems. Unlike a classical RF synthesizer, the proposed synthesizer frequency multiplication is performed by an intermediate frequency (IF) voltage-controlled oscillator (VCO) and a programmable- K frequency multiplier (FM). Therefore, an RFVCO gain, K_{\text{vco}} , is replaced by K_{\text{ifvco}} \ttimes K , where K_{\text{ifvco}} is the IFVCO gain. Consequent K_{\text{ifvco}} can be 95 times less than K_{\text{vco}} to cover the 3.2-5.6-GHz frequency band. The K_{\text{ifvco}} reduction will provide 21.6-dB phase noise (PN) improvement according to 20\log(K_{\text{vco}} \omega _{\text{if}} / K_{\text{ifvco}} \omega_{\text{rf}} ) . On the contrary, the proposed synthesizer has the same frequency divider (FD) in the feedback path as that of the classical fractional- N synthesizer. The synthesizer minimum channel resolution can be possibly 195.3125 kHz with a 200-MHz reference clock and 10-bit mash 1-1-1 \Delta \Sigma encoder. A bipolar junction transistor (BJT)-based charge pump (CP) is integrated to provide low in-band PN. The presented synthesizer is fabricated on a 130-nm SiGe process, and its core die size is 1 mm ^{\text{2}} . The total power consumption is 15 mW, as well as the channel resolution is 390.625 kHz to guarantee less than - 75 dBc fractional spur. The integrated rms jitter for the 1