A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has...

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Veröffentlicht in:2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 2002, Vol.1, p.76-77 vol.1
Hauptverfasser: Farjad-Rad, R., Dally, W., Hoik-Tiaq Ng, Poulton, J., Stone, T., Rathi, R., Lee, E., Huang, D., Nathan, R.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit noise
Clocks
Delay
Frequency
Jitter
Logic
Phase locked loops
Ring oscillators
Voltage control
Voltage-controlled oscillators
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Zusammenfassung:The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.
ISSN:0193-6530
DOI:10.1109/ISSCC.2002.992946